A power metal-oxide-semiconductor field effect transistor (MOSFET) device, featuring high integration density, high reliability, extremely low static current leakage and improving power handling capacity, is widely applied in consumer electronics, computers and other related sectors.
In the existing art, as shown in FIG. 1, when co-packaging a high-side metal-oxide-semiconductor field effect transistor (HS MOSFET) 2 and a low-side metal-oxide-semiconductor field effect transistor (LS MOSFET) 1, the HS MOSFET 2 and LS MOSFET 1 are installed on die pad 4 and die pad 3 of a leadframe respectively, and the connections from the top electrodes of LS MOSFET 1 and HS MOSFET 2 to the pins of the die pad, as well as the connection between the top source contact area of the HS MOSFET 2 and the bottom drain contact area of LS MOSFET 1 are realized through bond wires 5.
In the existing art, as shown in FIG. 2, a surface mounted capacitor 11 may be configured on the surface of the semiconductor package 12 to decrease parasitic inductance.
In the package of the abovementioned device, with the chips connected by bond wires, the resistance and inductance between the chips are increased; and with the capacitor mounted on semiconductor surface, the size and cost of the semiconductor package are also increased.